Improved method and apparatus for submicron IC design using edge fragment tagging to correct edge placement distortion
A Standard patent application filed on 13 March 2000 credited to Cobb, Nicolas Bailey
Details
Application number :
49708
Application type :
Standard
Application status :
LAPSED
Under opposition :
No
Proceeding type :
Invention title :
Improved method and apparatus for submicron IC design using edge fragment tagging to correct edge placement distortion
Inventor :
Cobb, Nicolas Bailey
Agent name :
Davies Collison Cave
Address for service :
Level 15 1 Nicholson Street MELBOURNE VIC 3000
Filing date :
13 March 2000
Associated companies :
Applicant name :
Mentor Graphics Corporation
Applicant address :
8005 S.W.Boeckman Road Wilsonville OR 97070 United States Of America