Method and apparatus using silicide layer for protecting integrated circuits from reverse engineering
A Standard patent application filed on 14 April 2000 credited to Baukus, James P. ; Clark, William M. Jr. ; Chow, Lap-Wai

Details

Application number :

42440  

Application type :

Standard  

Application status :

LAPSED  

Under opposition :

No  

Proceeding type :

 

Invention title :

Method and apparatus using silicide layer for protecting integrated circuits from reverse engineering  

Inventor :

Baukus, James P. ; Clark, William M. Jr. ; Chow, Lap-Wai  

Agent name :

 

Address for service :

 

Filing date :

14 April 2000  

Associated companies :

 

Applicant name :

HRL Laboratories, LLC  

Applicant address :

 

Old name :

 

Original Source :

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