Integrated circuits protected against reverse engineering and method for fabricating the same using etched passivation openings in passivation layer
A Standard patent application filed on 24 January 2002 credited to Baukus, James P. ; Clark, William M. Jr. ; Chow, Lap-Wai

Details

Application number :

2002236877  

Application type :

Standard  

Application status :

LAPSED  

Under opposition :

No  

Proceeding type :

 

Invention title :

Integrated circuits protected against reverse engineering and method for fabricating the same using etched passivation openings in passivation layer  

Inventor :

Baukus, James P. ; Clark, William M. Jr. ; Chow, Lap-Wai  

Agent name :

 

Address for service :

 

Filing date :

24 January 2002  

Associated companies :

 

Applicant name :

BAUKUS, James, P.  

Applicant address :

1718 Drumcliff Court, Westlake Village, CA 91361  

Old name :

 

Original Source :

Go  

Same Inventor

• Method and apparatus using silicide layer for protecting integrated...
• Cmos process
• Implanted hidden interconnections in a semiconductor device for...
• Integrated circuit with reverse engineering protection
• A conductive channel pseudo block process and circuit to inhibit...