Semiconductor fabrication process, lateral pnp transistor, and integrated circuit
A Standard patent application filed on 11 February 2003 credited to Johansson, Ted ; Norstrom, Hans

Details

Application number :

2003206338  

Application type :

Standard  

Application status :

LAPSED  

Under opposition :

No  

Proceeding type :

 

Invention title :

Semiconductor fabrication process, lateral pnp transistor, and integrated circuit  

Inventor :

Johansson, Ted ; Norstrom, Hans  

Agent name :

 

Address for service :

 

Filing date :

11 February 2003  

Associated companies :

 

Applicant name :

INFINEON TECHNOLOGIES AG  

Applicant address :

St.-Martin-Strasse 53 81669 Munchen Germany  

Old name :

 

Original Source :

Go  

Same Inventor

• Selective base etching
• Silicon-germanium mesa transistor
• Lateral pnp transistor device, integrated circuit, and fabrication...
• A method of forming base regions and emitter windows in silicon...
• An arrangement for preventing short-circuiting in a bipolar...