Vertical structure and process for semiconductor wafer-level chip scale packages
A Standard patent application filed on 06 April 2001 credited to Bhalla, Anup ; Lan, Bosco ; Chen, Changsheng ; Ho, Yueh-Se ; Korec, Jacek ; Lee, Shawn Luo ; Kasem, Y. Mohammed ; Tjhia, Eddy

Details

Application number :

2001251418  

Application type :

Standard  

Application status :

LAPSED  

Under opposition :

No  

Proceeding type :

 

Invention title :

Vertical structure and process for semiconductor wafer-level chip scale packages  

Inventor :

Bhalla, Anup ; Lan, Bosco ; Chen, Changsheng ; Ho, Yueh-Se ; Korec, Jacek ; Lee, Shawn Luo ; Kasem, Y. Mohammed ; Tjhia, Eddy  

Agent name :

 

Address for service :

 

Filing date :

06 April 2001  

Associated companies :

 

Applicant name :

Siliconix, Inc.  

Applicant address :

 

Old name :

 

Original Source :

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