System and method for generating fractional length delay lines in a digital signal processing system
A Standard patent application filed on 03 April 1997 credited to Van Duyne, Scott A.
;
Stilson, Timothy S.
;
Scandalis, Gregory P.
;
Jaffe, David A.
Details
Application number :
26600
Application type :
Standard
Application status :
CEASED
Under opposition :
No
Proceeding type :
Invention title :
System and method for generating fractional length delay lines in a digital signal processing system
Inventor :
Van Duyne, Scott A.
;
Stilson, Timothy S.
;
Scandalis, Gregory P.
;
Jaffe, David A.
Agent name :
Davies Collison Cave
Address for service :
Level 15 1 Nicholson Street MELBOURNE VIC 3000
Filing date :
03 April 1997
Associated companies :
Applicant name :
Board of Trustees for the Leland Stanford Junior University, The
Applicant address :
Suite 300 900 Welch Road Palo Alto California 94304 United States of America