A digital signal receiving circuit with means for controlling a baud rate sampling phase by a power of sampled signals
A Standard patent application filed on 16 November 1988 credited to Arai, Masanobu
;
Ogata, Takenori
;
Yamaguchi, Masaru
Details
Application number :
25612
Application type :
Standard
Application status :
CEASED
Under opposition :
No
Proceeding type :
Invention title :
A digital signal receiving circuit with means for controlling a baud rate sampling phase by a power of sampled signals