Method and circuit arrangement for synchronization of synchronously or asynchronously clocked processing units
A Standard patent application filed on 01 August 2003 credited to Weber, Anton ; Peleska, Pavel ; Schnabel, Dirk

Details

Application number :

2003255351  

Application type :

Standard  

Application status :

LAPSED  

Under opposition :

No  

Proceeding type :

 

Invention title :

Method and circuit arrangement for synchronization of synchronously or asynchronously clocked processing units  

Inventor :

Weber, Anton ; Peleska, Pavel ; Schnabel, Dirk  

Agent name :

 

Address for service :

 

Filing date :

01 August 2003  

Associated companies :

 

Applicant name :

SIEMENS AKTIENGESELLSCHAFT  

Applicant address :

Wittelsbacherplatz 2, 80333 Munchen  

Old name :

 

Original Source :

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