High-resolution multi-phase clock generator with an array-structured delay-locking loop
A Standard patent application filed on 06 May 2003 credited to Min, Byung Jun ; Jun, Hyun Duk ; Byun, Sang Jin ; Yang, Jeong Sik ; Kim, Jin Wook ; Kim, Hyun Jin

Details

Application number :
2003230251  
Application type :
Standard  
Application status :
LAPSED  
Under opposition :
No  
Proceeding type :
 
Invention title :
High-resolution multi-phase clock generator with an array-structured delay-locking loop  
Inventor :
Min, Byung Jun ; Jun, Hyun Duk ; Byun, Sang Jin ; Yang, Jeong Sik ; Kim, Jin Wook ; Kim, Hyun Jin  
Agent name :
 
Address for service :
 
Filing date :
06 May 2003  
Associated companies :
 
Applicant name :
BERKANA WIRELESS KOREA INC.  
Applicant address :
6 Donggwan, IT-venture-Tower Bldg.,, 78 Garak-dong, Songpa-gu, Seoul 138-160  
Old name :
 
Original Source :
Go  

Same Inventor