Bit liklihood calculation method and demodulation device
A Standard patent application filed on 10 March 2003 credited to Saito, Yoshiko ; Uesugi, Mitsuru

Details

Application number :

2003211861  

Application type :

Standard  

Application status :

LAPSED  

Under opposition :

No  

Proceeding type :

 

Invention title :

Bit liklihood calculation method and demodulation device  

Inventor :

Saito, Yoshiko ; Uesugi, Mitsuru  

Agent name :

 

Address for service :

 

Filing date :

10 March 2003  

Associated companies :

 

Applicant name :

MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.  

Applicant address :

1006, Oaza Kadoma, Kadoma-shi, Osaka 571-8501  

Old name :

 

Original Source :

Go  

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