A method and apparatus for generating a solid state circuit layout with in-design variability associated to the setting of analog signal processing parameters, and an integrated circuit design and an integrated circuit produced by applying such method
A Standard patent application filed on 01 July 2002 credited to Kasperkovitz, Wolfdietrich Georg

Details

Application number :
2002321161  
Application type :
Standard  
Application status :
LAPSED  
Under opposition :
No  
Proceeding type :
 
Invention title :
A method and apparatus for generating a solid state circuit layout with in-design variability associated to the setting of analog signal processing parameters, and an integrated circuit design and an integrated circuit produced by applying such method  
Inventor :
Kasperkovitz, Wolfdietrich Georg  
Agent name :
 
Address for service :
 
Filing date :
01 July 2002  
Associated companies :
 
Applicant name :
KASPERKOVITZ, Wolfdietrich, Georg  
Applicant address :
Eikenlaan 4, NL-5581 HA Waalre  
Old name :
 
Original Source :
Go  

Same Inventor