Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (dfd) techniques
A Standard patent application filed on 28 February 2002 credited to Hsu, Chi-Chan ; Chao, Hao-Jan ; Wang, Hsin-Po ; Lee, Jachee ; Wang, Laung-Terny ; Wen, Xiaoqing ; Chang, Ming-Tung ; Hsu, Po-Ching ; Tsai, Sen-Wei ; Kao, Shih-Chia ; Lin, Shyh-Horng ; Li

Details

Application number :

2002243849  

Application type :

Standard  

Application status :

LAPSED  

Under opposition :

No  

Proceeding type :

 

Invention title :

Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (dfd) techniques  

Inventor :

Hsu, Chi-Chan ; Chao, Hao-Jan ; Wang, Hsin-Po ; Lee, Jachee ; Wang, Laung-Terny ; Wen, Xiaoqing ; Chang, Ming-Tung ; Hsu, Po-Ching ; Tsai, Sen-Wei ; Kao, Shih-Chia ; Lin, Shyh-Horng ; Li  

Agent name :

 

Address for service :

 

Filing date :

28 February 2002  

Associated companies :

 

Applicant name :

SYNTEST TECHNOLOGIES, INC.  

Applicant address :

505 S. Pastoria Avenue, Suite 101, Sunnyvale, CA 94086  

Old name :

 

Original Source :

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