System and method for polishing and planarization of semiconductor wafers using reduced surface area polishing pads
A Standard patent application filed on 13 December 2001 credited to Boyd, John M. ; Gotkis, Yehiel ; Kistler, Rod

Details

Application number :

2002241637  

Application type :

Standard  

Application status :

LAPSED  

Under opposition :

No  

Proceeding type :

 

Invention title :

System and method for polishing and planarization of semiconductor wafers using reduced surface area polishing pads  

Inventor :

Boyd, John M. ; Gotkis, Yehiel ; Kistler, Rod  

Agent name :

 

Address for service :

 

Filing date :

13 December 2001  

Associated companies :

 

Applicant name :

LAM RESEARCH CORPORATION  

Applicant address :

4650 Cushing Parkway, Fremont, CA 94538  

Old name :

 

Original Source :

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