Method and apparatus for pipelining ordered input/output transactions in a cache coherent, multi-processor system
A Standard patent application filed on 14 August 2001 credited to Kumar, Akhilesh ; Khare, Manoj ; Looi, Lily ; Creta, Kenneth

Details

Application number :

2001281273  

Application type :

Standard  

Application status :

LAPSED  

Under opposition :

No  

Proceeding type :

 

Invention title :

Method and apparatus for pipelining ordered input/output transactions in a cache coherent, multi-processor system  

Inventor :

Kumar, Akhilesh ; Khare, Manoj ; Looi, Lily ; Creta, Kenneth  

Agent name :

 

Address for service :

 

Filing date :

14 August 2001  

Associated companies :

 

Applicant name :

Intel Corporation  

Applicant address :

 

Old name :

 

Original Source :

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